EPROMs and electrically erasable programmable read only memory (EEPROM) arrays arc basic building blocks of microprocessor systems. The EPROM and EEPROM arrays arc comprised of a plurality of EPROM or EEPROM cells, each of which must be individually activatable.
Over the years, EPROM and EEPROM arrays have been continually improved, both in speed and in density, thereby to enable the microprocessor systems to run complicated programs at faster speeds. Different architectures provide different densities and different operating speeds, where typically an improvement in speed comes at a cost of reduced density, and vice versa.
Some types of EPROM arrays arc common source arrays, virtual ground arrays, partitioned virtual ground arrays and alternate metal virtual ground arrays. Some types of EEPROM arrays are common source arrays and virtual ground arrays.
A virtual ground architecture is described in U.S. Pat. No. 4,267,632. In the '632 patent, a first plurality of parallel spaced-apart, polycrystalline silicon ("polysilicon") lines is defined on one surface of but insulated from, the silicon semiconductor substrate. Parallel, spaced apart doped regions ("diffusion bit lines") are formed in the silicon substrate between these first polysilicon ("poly 1") lines and in alignment with these lines. A second plurality of parallel, spaced-apart, polysilicon lines ("poly 2"), insulated from the poly 1 lines and the diffusion bit lines in the substrate, is formed perpendicular to the poly 1 lines and the diffusion bit lines. The poly 2 lines are then used as an etch mask to remove those portions of the poly 1 lines not covered by the poly 2 lines. The portions of the poly 1 lines remaining beneath the poly 2 lines are located between the diffusion bit lines and are the floating gates of the EPROM transistors, or cells.
While the '632 patent yields a plurality of floating gate devices in a relatively high density array, the cell size is still larger than desired. One reason for this is that one metal line is formed above each elongated diffusion bit line. Consequently, the size of the array is increased both by the widths of these metal lines and by the need to have numerous contacts (which of necessity are wider than the widths of the metal lines) between such metal lines and the underlying elongated diffusion bit lines. In addition, having a symmetrical transistor (source and drain are interchangeable) complicates the programming function in virtual ground arrays.
Furthermore, when reading a selected EPROM cell, the drain diffusion bit line is pre-charged to a predetermined level and the EPROM cell is read by removing charge from the drain line. It will be appreciated by those skilled in the art that the reading time is inversely dependent on the capacitance of the drain line and that the capacitance of each drain line is a function of the accumulation of the capacitance of the many EPROM cells attached to it.
Reference is now made to FIGS. 1A and 1B which illustrate a partitioned virtual ground architecture described in the article "A New Virtual Ground Array Architecture for Very High Speed, High Density EPROMs", presented at the 1991 VLSI Circuits Symposium, Japan by W. Kammerer, et al., employees of the common assignees of the present invention.
In this architecture, there are two types of alternating diffusion bit lines, segmented ones 22 and continuous ones 24. The segmentation is provided in order to reduce bit line capacitance and achieve thereby a high operating speed.
Each diffusion bit line 22 or 24 is associated with a metal line 20 or 21, respectively, and a contact 28 or 30, respectively. The segmented diffusions 22 are connected to the metal lines 20 and contacts 28 via n-channel select transistors 26.
The n-channel transistors 26 and contacts 28 are located in one area of the array and the contacts 30 are placed in a second area of the array, thereby to minimize the amount of space they utilize. The pitch of the partitioned virtual ground architecture is limited by the width of the transistor 26 and, due to the staggering of the contacts 28 and 30, by one-half contact 28 or 30.
Typically, developments in EPROM manufacturing processes have not decreased the metal pitch as much as the pitch of the poly 1 and poly 2 layers. Since the metal pitch is considerably larger than the minimum dimension of an EPROM cell and since the partitioned virtual ground architecture has one metal line per cell, the metal pitch is the limiting factor in the size of each cell.
To achieve a maximal operating speed during a read operation, the sensed bit line must have the least capacitance and therefore, must be one of the segmented diffusions 22. As a result, for reading, the segmented diffusions 22 are dedicated read lines and the continuous diffusions 24 are dedicated source lines. However, for programming, the arrangement described hereinabove docs not work since the n-channel transistors 26 cannot transfer the high voltage and high current required to program a cell. Therefore, during programming, the continuous diffusions 24 are dedicated to serve as high voltage terminals and the segmented diffusions 22 are dedicated to serve as source terminals.
Segmentation is also utilized for separating a flash EEPROM array into a plurality of isolated EEPROM areas. This architecture is described in U.S. Pat. No. 5,126,808, a copy of whose FIG. 5 is presented herein as FIG. 2 to whom reference is now made.
The segmented flash EEPROM architecture includes a plurality of EEPROM pages 100-k, each comprised of a multiplicity of flash EEPROM cells (ki,j), where k indicates the page number, i the row number and j the column number. The EEPROM cells (ki,j) are common ground array flash EEPROM transistors, wherein the sources S are connected to each other and to a ground signal.
The drain bit lines D are strapped by segmented metal lines BLk-j of a first metal layer. The rectal line segments BLk-j are the local bit lines. The segmented metal lines of a page k are connected to continuous second metal lines BLk, which are global bit lines, through n-channel select transistors (i,j). Due to the use of the local bit lines, only one local block k is connected to the global bit line at any one time. If there are eight local blocks and bit lines, this segmentation reduces the bit line capacitance by a factor of 8.
However, before an EPROM or EEPROM cell can be read, its drain must be pro-charged to a certain level. If no voltage is applied to a page of an EPROM or EEPROM array, the level of charge will slowly decay. Therefore, in the flash EEPROM architecture of U.S. Pat. No. 5,126,808, each page must first be pre-charged before the data stored therein can be sensed. This reduces the operating speed.
The flash EEPROM architecture described in U.S. Pat. No. 5,126,808 has one metal line and one contact for every diffusion bit line. Thus, the area of the flash EEPROM array of U.S. Pat. No. 5,126,808 is large and is limited by the metal pitch.
If there were only one metal line for every two diffusion bit lines and a contact, the limiting factor would not be the metal pitch, but rather the pitch of the polysilicon layers. This is known as a "poly pitch limited" architecture. One architecture which has only one such metal line is that of the alternating metal virtual ground EPROM array, described in U.S. Pat. Nos. 5,204,835 and 5,151,375, assigned to the common assignee of the present invention, and illustrated in FIG. 3 to which reference is now made. U.S. Pat. Nos. 5,204,835 and 5,151,375 are incorporated herein by reference.
The EPROM array of U.S. Pat. Nos. 5,151,375 and 5,204,835 comprises an EPROM area 50 comprising a plurality of EPROM transistors 52, or cells, surrounded by two "control areas" 54 comprising control elements, detailed hereinbelow.
In the EPROM area 50, each cell 52 comprises a gate 56, a source 58 and a drain 60. The sources 58 of a column of EPROM cells 52 together form non-metal-strapped, segmented diffusion bit lines, labeled S-1, S and S+1. The drains 60 of a column of EPROM cells 52 together form metal-strapped, continuous diffusion bit lines labeled M-1, M and M+1. Segmented bit lines S-1, S and S+1 typically connect together N EPROM cells 52, where N is typically 64. The gates 56 of a row of cells are connected to one word line WLi.
Each control area 54 comprises select transistors 62, contacts 66 and select lines SELn and SEL(n+1). Select transistors 62 are typically stacked gate transistors but can also be n-channel devices. One contact 66 is connected to each bit line M-1, M or M+1 in each control area 54.
A pair of select transistors 62 from the two control areas 54 controlling an EPROM area 50 are operative, when activated by the appropriate select lines SELn or SEL(n+1), to connect one segmented diffusion bit line S-1, S or S+1 to a neighboring continuous diffusion bit line M-1, M or M+1.
In order to access the EPROM cell labeled 52a, the following lines are activated: word line WL1, select lines SEL(n+1) and bit lines M and M-1. Bit line M receives the drain voltage and bit line M-1 receives the source voltage, which is typically a ground voltage. The select transistors 62 which are activated by select lines SEL(n+1) transfer the source voltage from bit line M-1 to the segment S-1. Word line WL1 activates a row of EPROM cells and bit lines M and M-1 activate a column of cells, thereby activating only EPROM cell 52a, which sits at the intersection of the activated row and colunm. The output of the EPROM cell 52a is provided through the contact 66 which is connected to the appropriate bit line.
In order to access the EPROM cell labeled 52b, voltage is placed on word line WL1, select lines SELn and metal strapped bit lines M-1 and M. Metal strapped bit lines M-1 and M become the drain and source, respectively, wherein the source is transferred to segment S-1 through the select transistors 62a.
It is noted that tim source is always transferred to the segment lines Sj. It can be seen that the metal strapped bit lines Mj act as sources whenever they are connected to a segment line and as drains otherwise.
It will further be appreciated that, when the select lines SEL(n+1) activate a row of select transistors 62, they connect each bit line Mj with a segmented bit line Sj. Thus, when reading EPROM cell 52a, metal strapped bit line M-1 is connected, through the select transistor labeled 62a, to the segmented bit line S-1. This transfers the source to bit line S-1. At the same time, metal strapped bit line M (the drain) is connected, through the select transistor labeled 62b, to the segmented bit line S. Thus, the capacitance of the drain line is the sum of capacitance of the metal strapped bit line M plus the capacitance of the segmented bit line S connected to it. The overall bit line capacitance in this architecture has no advantages or disadvantages relative to other prior art architectures. It has a smaller area but adds capacitance due to the fact that the diffusions are continuous across the array.
Therefore, although the alternating metal virtual ground architecture described in U.S. Pat. Nos. 5,204,835 and 5,151,375 has a very high density, its operating speed is slower than desired, due to the extensive capacitance of the operative drain line.